In general, clock generation circuits are used to clock synchronous digital circuits, such as analog to digital converters (ADCs). A clock generation circuit provides a repetitive signal having a constant period. A clock signal has a first phase and a second phase within a single period of the clock signal. Typically, a clock generation circuit provides both an inverting and non-inverting clock signal. Clock generation circuits also commonly provide delayed clock signals.
One type of clock signal is a non-overlapping clock signal. Non-overlapping clock signals are commonly used in switched capacitor integrator circuits. A non-overlapping clock generation circuit provides a non-inverting clock signal and inverting clock signal that respectively transition before a delayed non-inverting clock signal and a delayed inverting clock signal. There is also a delay between transitions of the non-inverting clock signal and the inverting clock signal. In general, non-overlapping clock signals are used to reduce voltage error in switched capacitor circuits.
Conventional non-overlapping clock generator circuits are well known in the art and are commonly used to generate the required non-overlapping clock signals for switched capacitor integrator circuits that process signals in the audio frequency range.
In a switched-capacitor integrator utilized in high-speed analog-to-digital converters (ADCs), non-overlapping clocks are used. However, non-overlap time and clock phase delay time are generally implemented with inverter delays. The inverter delays vary over process, supply voltage and temperature. For example, inverter delays may vary over a factor of two when process, operating supply voltage, and operating temperature variations are taken into account. Process variations occur during the manufacture of integrated circuits (ICs).
The worst case conditions of process, operation voltage and temperature conditions are called slow and fast corner conditions. The non-overlap time requirements at a fast corner condition need to be satisfied which may yield two times the non-overlap time in a slow corner condition. The extra non-overlap time and phase delay time in a slow corner condition consumes the active time of the clock and requires faster settling of a switched capacitor integrator. Hence, there is more current consumption for an operational transconductance amplifier within the switch-capacitor integrator. Furthermore, as the switching-capacitor integrator sampling frequency (fs) increases, non-overlap time and phase delay becomes more significant relative to the active time of the clocking signal.
There is therefore a need for techniques for generating precise non-overlap time and clock phase delay time even at high switching-capacitor integrator sampling (Fs) frequencies.